`include "define.sv"

module apb_slave (
    input  wire         PCLK,
    input  wire         PRESETn,
    input  wire [31:0]  PADDR,
    input  wire         PWRITE,
    input  wire [31:0]  PWDATA,
    input  wire         PENABLE,
    input  wire         PSEL,
    output reg  [31:0] PRDATA,
    output reg          PREADY,
    output reg          PSLVERR,
    output reg  [1:0]  matrix_type,
    output reg  [1:0]  data_type,
    output reg  [1:0]  mix_precision
);

    always @(posedge PCLK or negedge PRESETn) begin
        if (!PRESETn) begin
            matrix_type <= 2'b00;
            data_type   <= 2'b00;
            mix_precision <= 2'b00;
            PRDATA      <= 32'h0;
            PREADY      <= 1'b0;
            PSLVERR     <= 1'b0; 
        end else begin
            if (PSEL && PENABLE) begin
                if (PWRITE) begin
                    if (PADDR == 32'h0000_0004) begin
                        matrix_type <= PWDATA[3:2];
                        data_type   <= PWDATA[1:0];
                        mix_precision <= PWDATA[5:4];
                    end
                    PREADY <= 1'b1;
                end else begin
                    if (PADDR == 32'h0000_0004) begin
                        PRDATA <= {mix_precision, matrix_type, data_type};
                    end else begin
                        PRDATA <= 32'h0; 
                    end
                    PREADY <= 1'b1;
                end
            end else begin
                PREADY <= 1'b0;
                PRDATA <= 32'h0;
            end
        end
    end
endmodule